MC68HC908AT32 Datasheet, PDF (150/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface Module (SCI)
• Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the
receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver
does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit,
ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start
bit or after the stop bit.
NOTE
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
16.4.3.7 Receiver Interrupts
These sources can generate CPU interrupt requests from the SCI receiver:
• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
CPU interrupts.
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in
from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
16.4.3.8 Error Interrupts
These receiver error flags in SCS1 can generate CPU interrupt requests:
• Receiver overrun (OR) — The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate SCI error CPU interrupt requests.
• Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
• Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects
a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error
CPU interrupt requests.
• Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.
16.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
16.5.1 Wait Mode
The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module
can bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
MC68HC908AT32 Data Sheet, Rev. 3.1
150
Freescale Semiconductor