MC68HC908AT32 Datasheet, PDF (205/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
Addr.
Register Name
$0045
Timer B CH0 Status and Control ^Read:
Register (TBSC0) Write:
See page 215. _Reset:
Read:
$0046
Timer B CH0 Register High (TBCH0H)
See page 218.
Write:
Reset:
$0047
Read:
Timer B CH0 Register Low (TBCH0L)
See page 218.
Write:
Reset:
$0048
Timer B CH1 Status and Control ^Read:
Register (TBSC1) Write:
See page 215. _Reset:
Read:
$0049
Timer B CH1 Register High (TBCH1H)
See page 218.
Write:
Reset:
$004A
Read:
Timer B CH1 Register Low (TBCH1L)
See page 218.
Write:
Reset:
Bit 7
CH0F
0
0
Bit 15
Bit 7
CH1F
0
0
Bit 15
Bit 7
R
6
5
4
3
2
CH0IE MS0B MS0A ELS0B ELS0A
0
0
0
0
0
14
13
12
11
10
Indeterminate after reset
6
5
4
3
2
CH1IE
0
Indeterminate after reset
0
MS1A ELS1B ELS1A
R
0
0
0
0
14
13
12
11
10
Indeterminate after reset
6
5
4
3
2
= Reserved
Indeterminate after reset
Figure 19-2. TIMB I/O Register Summary (Continued)
1
Bit 0
TOV0 CH0MAX
0
0
9
Bit 8
1
Bit 0
TOV1 CH1MAX
0
0
9
Bit 8
1
Bit 0
19.3.1 TIMB Counter Prescaler
The TIMB clock source can be one of the seven prescaler outputs or the TIMB clock pin,
PTD4/ATD12/TBCLK. The prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIMB status and control register select the TIMB clock source.
19.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0 through TBSC1
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIMB latches the contents of the TIMB counter into the TIMB channel
registers, TCHxH–TCHxL. Input captures can generate TIMB CPU interrupt requests. Software can
determine that an input capture event has occurred by enabling input capture interrupts or by polling the
status flag bit.
The result obtained by an input capture will be two more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal
synchronization.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
205