MC68HC908AT32 Datasheet, PDF (108/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
unstable. Also, always choose a capacitor with a tight tolerance (±20 percent or better) and low
dissipation.
8.9.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the equations below. These equations yield
nominal values under the following conditions:
• Correct selection of filter capacitor, C_F. See 8.9.3 Choosing a Filter Capacitor.
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters. K_ACQ is the K factor when the PLL
is configured in acquisition mode, and K_TRK is the K factor when the PLL is configured in tracking mode.
See 8.3.2.2 Acquisition and Tracking Modes.
tACQ
=
⎛
⎜
⎝
V--f--R-D---D-D----V-A---_{⎠⎟⎞}
⎛
⎝
K-----A---8-C-----Q---^⎠⎞
tAL
=
⎝⎜⎛ ^{V--f--R-D---D-D----V-A---}⎠⎟⎞
⎛
⎝
K-----T--4--R----K---^⎠⎞
tLock = tACQ + tAL
Note the inverse proportionality between the lock time and the reference frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. (See 8.3.2.3 Manual and Automatic PLL Bandwidth Modes.) A certain number of
clock cycles, n_ACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆_TRK,
before exiting acquisition mode. A certain number of clock cycles, n_TRK, is required to ascertain that the
PLL is within the lock mode entry tolerance, ∆_Lock. Therefore, the acquisition time, t_ACQ, is an integer
multiple of n_ACQ/f_RDV, and the acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_RDV.
Also, since the average frequency over the entire measurement period must be within the specified
tolerance, the total time usually is longer than t_Lock as calculated previously.
In manual mode, it is usually necessary to wait considerably longer than t_Lock before selecting the PLL
clock (see 8.3.3 Base Clock Selector Circuit) because the factors described in 8.9.2 Parametric
Influences on Reaction Time may slow the lock time considerably.
MC68HC908AT32 Data Sheet, Rev. 3.1
108
Freescale Semiconductor