MC68HC908AT32 Datasheet, PDF (324/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MC68HC08AS20 Emulator Input/Output Ports
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-4 summarizes the operation of the port D pins.
Table 27-4. Port D Pin Functions
DDRD PTD
Bit
Bit
I/O Pin
Mode
Accesses
to DDRD
Read/Write
Accesses to PTD
Read
Write
0
X
Input, Hi-Z
DDRD[6:0]
Pin
PTD[6:0]⁽¹⁾
1
X
Output
DDRD[6:0]
PTD[6:0]
PTD[6:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
27.6 Port E
Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA),
two of its pins with the serial communications interface module (SCI), and four of its pins with the serial
peripheral interface module (SPI).
27.6.1 Port E Data Register
The port E data register contains a data latch for each of the eight port E pins.
Address: $0008
Bit 7
Read:
PTE7
Write:
Reset:
Alternate Function: SPSCK
6
PTE6
MOSI
5
PTE5
MISO
4
3
PTE4
PTE3
Unaffected by reset
SS
TACH1
2
PTE2
TACH0
1
PTE1
RxD
Bit 0
PTE0
TxD
Figure 27-14. Port E Data Register (PTE)
PTE[7:0] — Port E Data Bits
PTE[7:0] are read/write, software programmable bits. Data direction of each port E pin is under the
control of the corresponding bit in data direction register E.
SPSCK — SPI Serial Clock Bit
The PTE7/SPSCK pin is the serial clock input of an SPI slave module and serial clock output of an SPI
master module. When the SPE bit is clear, the PTE7/SPSCK pin is available for general-purpose I/O.
MOSI — Master Out/Slave In Bit
The PTE6/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear,
the PTE6/MOSI pin is available for general-purpose I/O. See 17.13.1 SPI Control Register.
MISO — Master In/Slave Out Bit
The PTE5/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit,
SPE, is clear, the SPI module is disabled, and the PTE5/MISO pin is available for general-purpose I/O.
See 17.13.1 SPI Control Register.
MC68HC908AT32 Data Sheet, Rev. 3.1
324
Freescale Semiconductor