MC68HC908AT32 Datasheet, PDF (52/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

FLASH Memory
FDIV0 — Frequency Divide Control Bit
This read/write bit together with FDIV1 selects the factor by which the charge pump clock is divided
from the system clock. See 4.4 Charge Pump Frequency Control.
BLK1— Block Erase Control Bit
This read/write bit together with BLK0 allows erasing of blocks of varying size. See 4.5 FLASH Erase
Operation for a description of available block sizes.
BLK0 — Block Erase Control Bit
This read/write bit together with BLK1 allows erasing of blocks of varying size. See 4.5 FLASH Erase
Operation for a description of available block sizes.
HVEN — High-Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the memory for either program or
erase operation. It can be set only if either PGM or ERASE is high and the sequence for erase or
program/verify is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
VERF — Verify Control Bit
This read/write bit configures the memory for verify operation. It cannot be set if the HVEN bit is high,
and if it is high when HVEN is set, it will automatically return to 0.
1 = Verify operation selected
0 = Verify operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. It is interlocked with the PGM bit such
that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. It is interlocked with the ERASE bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
4.4 Charge Pump Frequency Control
The internal charge pump is designed to operate at greatest efficiency at a frequency of 2 MHz. Table 4-1
shows how the FDIV bits are used to select a charge pump frequency and the recommended bus
frequency ranges for each configuration. Program and erase operations cannot be performed if the pump
clock frequency is below 2 MHz.
FDIV1
0
0
1
1
Table 4-1. Charge Pump Clock Frequency
FDIV0
0
1
0
1
Pump Clock Frequency
Bus frequency ÷ 1
Bus frequency ÷ 2
Bus frequency ÷ 2
Bus frequency ÷ 4
Bus Frequency
2 MHz ± 10%
4 MHz ± 10%
4 MHz ± 10%
8 MHz ± 10%
MC68HC908AT32 Data Sheet, Rev. 3.1
52
Freescale Semiconductor