MC68HC908AT32 Datasheet, PDF (330/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller-Digital (BDLC-D)
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 28-1. BDLC Block Diagram
Addr.
$003B
$003C
$003D
$003E
$003F
Name
Bit 7
6
5
4
3
2
BDLC Analog and Round-Trip ^Read: _ATE
RXPOL
0
Delay Register (BARD) Write:
See page 347. _{Reset: 1}
1
0
0
BO3
BO2
0
0
1
BDLC Control Register 1 ^Read: _IMSG
CLKS
R1
R0
0
0
(BCR1) Write:
R
R
See page 348. _{Reset: 1}
1
1
0
0
0
BDLC Control Register 2 ^Read:
(BCR2) Write:
See page 349. _Reset:
ALOOP
1
DLOOP
1
RX4XE
0
NBFS
0
TEOD
0
TSIFR
0
BDLC State Vector Register ^{Read: 0}
0
I3
I2
I1
I0
(BSVR) Write:
See page 354. _{Reset: 0}
0
0
0
0
0
BDLC Data Register ^Read: _BD7
BD6
BD5
BD4
BD3
BD2
(BDR) Write:
See page 355. _Reset:
Indeterminate after reset
= Unimplemented
R = Reserved
1
Bit 0
BO1
BO0
1
1
IE
WCM
0
0
TMIFR1 TMIFR0
0
0
0
0
0
0
BD1
BD0
Table 28-1. BDLC Input/Output (I/O) Register Summary
MC68HC908AT32 Data Sheet, Rev. 3.1
330
Freescale Semiconductor