MC68HC908AT32 Datasheet, PDF (93/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8
Clock Generator Module (CGM)
8.1 Introduction
The clock generator module (CGM) generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the
system clocks are derived. CGMOUT is based on either the crystal clock divided by two or the
phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency generator designed
for use with 1-MHz to 16-MHz crystals or ceramic resonators. The PLL can generate an 8-MHz bus
frequency without using a 32-MHz crystal.
8.2 Features
Features of the CGM include:
• Phase-locked loop with output frequency in integer multiples of the crystal reference
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• CPU interrupt on entry or exit from locked condition
8.3 Functional Description
The CGM consists of three major submodules:
• Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency
clock, CGMXCLK.
• Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock
CGMVCLK.
• Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The system clocks
are derived from CGMOUT.
Figure 8-1 shows the structure of the CGM.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
93