MC68HC908AT32 Datasheet, PDF (253/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Message Storage
completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages.
Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to
the transmit interrupt.
A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message
being sent and as such reduces the reactiveness requirements on the CPU. Problems may arise if the
sending of a message would be finished just while the CPU re-loads the second buffer. In that case, no
buffer would then be ready for transmission and the bus would be released.
Under all circumstances, at least three transmit buffers are required to meet the first of the above
requirements. The MSCAN08 has three transmit buffers.
The second requirement calls for some sort of internal prioritization which the MSCAN08 implements with
the “local priority” concept described in 23.4.2 Receive Structures.
23.4.2 Receive Structures
The received messages are stored in a 2-stage input first in first out (FIFO). The two message buffers are
mapped using a Ping Pong arrangement into a single memory area (see Figure 23-2). While the
background receive buffer (RxBG) is exclusively associated to the MSCAN08, the foreground receive
buffer (RxFG) is addressable by the CPU08. This scheme simplifies the handler software, because only
one address area is applicable for the receive process.
Each buffer has 13 bytes to store the CAN control bits, the identifier (standard or extended), and the data
content (for details, see 23.12 Programmer’s Model of Message Storage).
The receiver full flag (RXF) in the MSCAN08 receiver flag register (CRFLG) (see 23.13.5 MSCAN08
Receiver Flag Register) signals the status of the foreground receive buffer. When the buffer contains a
correctly received message with matching identifier, this flag is set.
After the MSCAN08 successfully receives a message into the background buffer, it copies the content of
RxBG into RxFG⁽¹⁾, sets the RXF flag, and emits a receive interrupt to the CPU⁽²⁾. A new message, which
may follow immediately after the IFS field of the CAN frame, will be received into RxBG.
The user’s receive handler has to read the received message from RxFG and to reset the RXF flag to
acknowledge the interrupt and to release the foreground buffer.
An overrun condition occurs when both the foreground and the background receive message buffers that
are filled with correctly received messages and another message is being received from the bus. The
latter message will be discarded and an error interrupt with overrun indication will occur if enabled. The
over-writing of the background buffer is independent of the identifier filter function. In the overrun situation,
the MSCAN08 will stay synchronized to the CAN bus. While it is able to transmit messages, all incoming
messages will be discarded.
NOTE
MSCAN08 will receive its own messages into the background receive
buffer RxBG but will not overwrite RxFG and will NOT emit a receive
interrupt. It also will not acknowledge (ACK) its own messages on the CAN
bus. The only exception to this rule is in loop-back mode when MSCAN08
will treat its own messages exactly like all other incoming messages.
1. Only if the RXF flag is not set.
2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
253