MC68HC908AT32 Datasheet, PDF (351/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC CPU Interface
TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response Control Bits
These three bits control the type of in-frame response being sent. The programmer should not set
more than one of these control bits to a 1 at any given time. However, if more than one of these three
control bits are set to 1, the priority encoding logic will force these register bits to a known value as
shown in Table 28-5. For example, if 011 is written to TSIFR, TMIFR1, and TMIFR0, then internally
they will be encoded as 010. However, when these bits are read back, they will read 011.
Table 28-5. BDLC Transmit In-Frame Response
Control Bit Priority Encoding
Write/Read
TSIFR
0
1
0
0
Write/Read
TMIFR1
0
X
1
0
Write/Read
TMIFR0
0
X
X
1
Actual
TSIFR
0
1
0
0
Actual
TMIFR1
0
0
1
0
Actual
TMIFR0
0
0
0
1
The BDLC supports the in-frame response (IFR) feature of J1850 by setting these bits correctly. The
four types of J1850 IFR are shown in Figure 28-18. The purpose of the in-frame response modes is to
allow multiple nodes to acknowledge receipt of the data by responding with their personal ID or
physical address in a concatenated manner after they have seen the EOD symbol. If transmission
arbitration is lost by a node while sending its response, it continues to transmit its ID/address until
observing its unique byte in the response stream. For VPW modulation, the first bit of the IFR is always
passive; therefore, an active normalization bit must be generated by the responder and sent prior to
its ID/address byte. When there are multiple responders on the J1850 bus, only one normalization bit
is sent which assists all other transmitting nodes to sync their responses.
TSIFR — Transmit Single Byte IFR with No CRC (Type 1 or 2) Bit
The TSIFR bit is used to request the BDLC to transmit the byte in the BDLC data register (BDR) as a
single byte IFR with no CRC. Typically, the byte transmitted is a unique identifier or address of the
transmitting (responding) node. See Figure 28-18.
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
has been received the BDLC will attempt to transmit the appropriate normalization bit followed
by the byte in the BDR.
0 = The TSIFR bit will be cleared automatically, once the BDLC
has successfully transmitted the byte in the BDR onto the
bus, or TEOD is set, or an error is detected on the bus.
If the programmer attempts to set the TSIFR bit immediately after the EOD symbol has been received
from the bus, the TSIFR bit will remain in the reset state and no attempt will be made to transmit the IFR
byte.
If a loss of arbitration occurs when the BDLC attempts to transmit and after the IFR byte winning
arbitration completes transmission, the BDLC will again attempt to transmit the BDR (with no
normalization bit). The BDLC will continue transmission attempts until an error is detected on the bus, or
TEOD is set, or the BDLC transmission is successful.
If loss of arbitration occurs in the last two bits of the IFR byte, two additional 1 bits will not be sent out
because the BDLC will attempt to retransmit the byte in the transmit shift register after the IRF byte
winning arbitration completes transmission.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
351