MC68HC908AT32 Datasheet, PDF (298/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface (TIM-6)
25.8 I/O Registers
These I/O registers control and monitor TIMA operation:
• TIMA status and control register (TASC)
• TIMA control registers (TACNTH–TACNTL)
• TIMA counter modulo registers (TAMODH–TAMODL)
• TIMA channel status and control registers (TASC0, TASC1, TASC2, TASC3, TASC4, and TSAC5)
• TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L, TACH2H–TACH2L,
TACH3H–TACH3L, TACH4H–TACH4L, and TACH5H–TACH5L)
25.8.1 TIMA Status and Control Register
The TIMA status and control register:
• Enables TIMA overflow interrupts
• Flags TIMA overflows
• Stops the TIMA counter
• Resets the TIMA counter
• Prescales the TIMA counter clock
Address: $0020
Bit 7
6
5
4
3
Read: TOF
0
0
TOIE TSTOP
Write: 0
TRST
R
2
1
Bit 0
PS2
PS1
PS0
Reset: 0
0
1
0
0
0
0
0
R
= Reserved
Figure 25-4. TIMA Status and Control Register (TASC)
TOF — TIMA Overflow Flag
This read/write flag is set when the TIMA counter resets to $0000 after reaching the modulo value
programmed in the TIMA counter modulo registers. Clear TOF by reading the TIMA status and control
register when TOF is set and then writing a logic 0 to TOF. If another TIMA overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1
to TOF has no effect.
1 = TIMA counter has reached modulo value.
0 = TIMA counter has not reached modulo value.
TOIE — TIMA Overflow Interrupt Enable Bit
This read/write bit enables TIMA overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIMA overflow interrupts enabled
0 = TIMA overflow interrupts disabled
MC68HC908AT32 Data Sheet, Rev. 3.1
298
Freescale Semiconductor