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MC68HC908AT32 Datasheet, PDF (361/378 Pages) Freescale Semiconductor, Inc – Microcontrollers
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29.4 5.0-Volt DC Electrical Characteristics
5.0-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage
(ILoad = –2.0 mA) all ports
Output low voltage
(ILoad = 1.6 mA) all ports
Input high voltage
All ports, IRQs, RESET, OSC1
VOH
VDD –0.8
—
—
V
VOL
—
—
0.4
V
VIH
0.7 x VDD
—
VDD
V
Input low voltage
All ports, IRQs, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
VDD + VDDA supply current
Run(3)
Wait(4)
Stop(5)
25°C
–40°C to +125°C
25°C with LVI enabled
–40°C to +125°C with LVI enabled
—
—
30
mA
—
—
15
mA
IDD
—
—
5
µA
—
—
50
µA
—
—
400
µA
—
—
500
µA
I/O ports Hi-Z leakage current
Input current
Capacitance
Ports (as input or output)
Low-voltage reset inhibit
Low-voltage reset inhibit/recover hysteresis
POR re-arm voltage(6)
POR reset voltage(7)
IL
IIn
COut
CIn
VLVII
HLVI
VPOR
VPORRST
—
—
±1
µA
—
—
±1
µA
—
—
—
—
12
8
pF
—
4.2
—
V
—
200
—
mV
0
—
200
mV
0
—
800
mV
POR rise time ramp rate(8)
RPOR
0.02
—
—
V/ms
High COP disable voltage(9)
VHI
VDD
VDD + 2
V
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all
modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dcloads. Less than 100 pF
on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. Measured with all modules
enabled.
5. Stop IDD measured with OSC1 = VSS.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.
9. See 13.8 COP Module during Break Interrupts.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
361
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