MC68HC908AT32 Datasheet, PDF (84/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
7.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 7-8 shows
interrupt entry timing. Figure 7-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See Figure 7-10.
MODULE
INTERRUPT
IAB
IDB
R/W
MODULE
INTERRUPT
IAB
IDB
R/W
LAST
ADDRESS
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECTOR VECTOR
ADDR. HIGH ADDR. LOW
NEW PC
NEW PC
+1
END OF PC – 1
PC – 1
LAST INSTR. LOW BYTE HIGH BYTE
X
A
CCR
VECTOR
HIGH
VECTOR
LOW
OPCODE
Figure 7-8. Interrupt Entry Timing
RTI
RTI
ADDRESS ADDR. + 1
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
RTI IRRELEVANT
OPCODE DATA
CCR
A
X
PC – 1
PC – 1
HIGH BYTE LOW BYTE
OPCODE
OPERAND
Figure 7-9. Interrupt Recovery Timing
MC68HC908AT32 Data Sheet, Rev. 3.1
84
Freescale Semiconductor