MC68HC908AT32 Datasheet, PDF (333/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC MUX Interface
28.4 BDLC MUX Interface
The MUX interface is responsible for bit encoding/decoding and digital noise filtering between the protocol
handler and the physical interface.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 28-3. BDLC Block Diagram
28.4.1 Rx Digital Filter
The receiver section of the BDLC includes a digital low pass filter to remove narrow noise pulses from the
incoming message. An outline of the digital filter is shown in Figure 28-4.
RX DATA
FROM
PHYSICAL
INTERFACE
(BDRXD)
INPUT
SYNC
DQ
4-BIT UP/DOWN COUNTER
UP/DOWN
OUT
DATA
LATCH
DQ
FILTERED
RX DATA OUT
MUX
INTERFACE
CLOCK
Figure 28-4. BDLC Rx Digital Filter Block Diagram
28.4.1.1 Operation
The clock for the digital filter is provided by the MUX interface clock (see f_BDLC parameter in Table 28-4).
At each positive edge of the clock signal, the current state of the receiver physical interface (BDRxD)
signal is sampled. The BDRxD signal state is used to determine whether the counter should increment or
decrement at the next negative edge of the clock signal.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
333