MC68HC908AT32 Datasheet, PDF (349/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC CPU Interface
IE— Interrupt Enable Bit
This bit determines whether the BDLC will generate CPU interrupt requests in run mode. It does not
affect CPU interrupt requests when exiting the BDLC stop or BDLC wait modes. Interrupt requests will
be maintained until all of the interrupt request sources are cleared by performing the specified actions
upon the BDLC’s registers. Interrupts that were pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not want to use the interrupt capability of the BDLC, the BDLC state vector
register (BSVR) can be polled periodically by the programmer to determine BDLC states. See 28.6.4
BDLC State Vector Register for a description of the BSVR.
WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode. See 28.7.2 Stop Mode and
28.7.1 Wait Mode for more details on its use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
28.6.3 BDLC Control Register 2
This register controls transmitter operations of the BDLC. It is recommended that BSET and BCLR
instructions be used to manipulate data in this register to ensure that the register’s content does not
change inadvertently.
Address: $003D
Bit 7
6
5
4
3
2
1
Read:
Write:
Reset:
ALOOP
1
DLOOP
1
RX4XE
0
NBFS
0
TEOD
0
TSIFR
0
TMIFR1
0
Figure 28-17. BDLC Control Register 2 (BCR2)
Bit 0
TMIFR0
0
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the analog physical interface’s final drive
stage. The programmer can use this bit to reset the BDLC state machine to a known state after the
off-chip analog transceiver is placed in loopback mode. When the user clears ALOOP, to indicate that
the off-chip analog transceiver is no longer in loopback mode, the BDLC waits for an EOF symbol
before attempting to transmit. Most transceivers have the ALOOP feature available.
1 = Input to the analog physical interface’s final drive stage is looped back to the BDLC receiver.
The J1850 bus is not driven.
0 = The J1850 bus will be driven by the BDLC. After the bit is cleared, the BDLC requires the bus
to be idle for a minimum of end-of-frame symbol time (t_TRV4) before message reception or a
minimum of inter-frame symbol time (t_TRV6) before message transmission. (See 29.14 BDLC
Receiver VPW Symbol Timings.)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
349