MC68HC908AT32 Datasheet, PDF (226/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC-8)
INTERNAL
DATA BUS
READ DDRB/DDRB
WRITE DDRB/DDRD
RESET
WRITE PTB/PTD
READ PTB/PTD
DDRBx
PTBx
ADC DATA REGISTER
DISABLE
PTBx
ADC CHANNEL x
DISABLE
CONVERSION
INTERRUPT ^COMPLETE
LOGIC
AIEN
COCO
CGMXCLK
BUS CLOCK
ADC VOLTAGE IN
ADC
ADCVIN
ADCH[4:0]
CHANNEL
SELECT
ADC CLOCK
CLOCK
GENERATOR
ADIV[2:0] ADICLK
Figure 21-1. ADC Block Diagram
21.3.2 Voltage Conversion
When the input voltage to the ADC equals V_REFH (see 29.6 ADC Characteristics), the ADC converts the
signal to $FF (full scale). If the input voltage equals V_SSA, the ADC converts it to $00. Input voltages
between V_REFH and V_SSA are a straight-line linear conversion. All other input voltages will result in $FF if
greater than V_REFH and $00 if less than V_SSA.
NOTE
Input voltage should not exceed the analog supply voltages.
21.3.3 Conversion Time
Conversion starts after a write to the ADSCR (ADC status control register, $0038) and requires between
16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For example,
with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
MC68HC908AT32 Data Sheet, Rev. 3.1
226
Freescale Semiconductor