MC68HC908AT32 Datasheet, PDF (339/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC MUX Interface
64 µs
200 µs
128 µs
ACTIVE
(1) INVALID PASSIVE BIT
PASSIVE
a
ACTIVE
(2) VALID PASSIVE LOGIC 0
PASSIVE
a
b
ACTIVE
(3) VALID PASSIVE LOGIC 1
PASSIVE
ACTIVE
b
c
(4) VALID EOD SYMBOL
PASSIVE
c
d
Figure 28-7. J1850 VPW Received Passive Symbol Times
Valid Passive Logic 0
See Figure 28-7(2). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between a and b, the current bit would be considered a logic 0.
Valid Passive Logic 1
See Figure 28-7(3). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between b and c, the current bit would be considered a logic 1.
Valid EOD Symbol
See Figure 28-7(4). If the passive-to-active received transition beginning the next data bit (or symbol)
occurs between c and d, the current symbol would be considered a valid end-of-data symbol (EOD).
300 µs
280 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(1) VALID EOF SYMBOL
a
b
(2) VALID EOF+
IFS SYMBOL
c
d
Figure 28-8. J1850 VPW Received Passive
EOF and IFS Symbol Times
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
339