MC68HC908AT32 Datasheet, PDF(129/378 Page) Freescale Semiconductor, Inc – Microcontrollers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC68HC908AT32 Datasheet, PDF (129/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

◁

Chapter 14

Low-Voltage Inhibit (LVI)

14.1 Introduction

This section describes the low-voltage inhibit (LVI) module (LVI47, Version A), which monitors the voltage

on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage.

14.2 Features

Features of the LVI module include:

â¢ Programmable LVI reset

â¢ Programmable power consumption

â¢ Digital filtering of VDD pin level

14.3 Functional Description

Figure 14-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module

contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to

monitor VDD voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when VDD

falls below a voltage, LVITRIPF, and remains at or below that level for nine or more consecutive CPU

cycles. LVISTOP, enables the LVI module during stop mode. This will ensure when the STOP instruction

is implemented, the LVI will continue to monitor the voltage level on VDD. LVIPWR, LVISTOP, and

LVIRST are in the configuration register (CONFIGA). (See Chapter 9 Configuration Register

(CONFIG-1).) Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage,

LVITRIPR. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset. (See 14.3.2

Forced Reset Operation.) The output of the comparator controls the state of the LVIOUT flag in the LVI

status register (LVISR).

An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.

14.3.1 Polled LVI Operation

In applications that can operate at VDD levels below the LVITRIPF level, software can monitor VDD by

polling the LVIOUT bit. In the configuration register, the LVIPWR bit must be at logic 0 to enable the LVI

module, and the LVIRST bit must be at logic 1 to disable LVI resets.

14.3.2 Forced Reset Operation

In applications that require VDD to remain above the LVITRIPF level, enabling LVI resets allows the LVI

module to reset the MCU when VDD falls to the LVITRIPF level and remains at or below that level for nine

or more consecutive CPU cycles. In the configuration register, the LVIPWR and LVIRST bits must be at

logic 0 to enable the LVI module and to enable LVI resets.

MC68HC908AT32 Data Sheet, Rev. 3.1

Freescale Semiconductor

129

▷