MC68HC908AT32 Datasheet, PDF (341/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

BDLC MUX Interface
Valid Active Logic 0
In Figure 28-9(3), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between b and c, the current bit would be considered a logic 0.
Valid SOF Symbol
In Figure 28-9(4), if the active-to-passive received transition beginning the next data bit (or symbol)
occurs between c and d, the current symbol would be considered a valid SOF symbol.
Valid BREAK Symbol
In Figure 28-10, if the next active-to-passive received transition does not occur until after e, the current
symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be transmitted onto the J1850 bus. See
28.4.2 J1850 Frame Format for BDLC response to BREAK symbols.
240 µs
ACTIVE
(2) VALID BREAK SYMBOL
PASSIVE
e
Figure 28-10. J1850 VPW Received BREAK Symbol Times
28.4.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-destructive manner, allowing the
message with the highest priority to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that another message is in progress, it waits
until the bus is idle. However, if multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF symbol and continue with each bit
thereafter. If a write to the BDR (for instance, to initiate transmission) occurred on or before
104 • t_BDLC from the received rising edge, then the BDLC will transmit and arbitrate for the bus. If a CPU
write to the BDR occurred after
104 • t_BDLC from the detection of the rising edge, then the BDLC will not transmit, but will wait for the next
IFS period to expire before attempting to transmit the byte.
The variable pulse-width modulation (VPW) symbols and J1850 bus electrical characteristics are chosen
carefully so that a logic 0 (active or passive type) will always dominate over a logic 1 (active or passive
type) simultaneously transmitted. Hence, logic 0s are said to be dominant and logic 1s are said to be
recessive.
Whenever a node detects a dominant bit on BDRxD when it transmitted a recessive bit, it loses arbitration
and immediately stops transmitting. This is known as bitwise arbitration.
Since a logic 0 dominates a logic 1, the message with the lowest value will have the highest priority and
will always win arbitration. For instance, a message with priority 000 will win arbitration over a message
with priority 011.
This method of arbitration will work no matter how many bits of priority encoding are contained in the
message.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
341