MC68HC908AT32 Datasheet, PDF (321/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port C
27.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to
a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output
buffer.
Address: $0006
Bit 7
6
Read:
0
MCLKEN
Write:
R
5
4
3
2
1
0
DDRC4 DDRC3 DDRC2 DDRC1
R
Reset: 0
0
0
0
0
0
0
R
= Reserved
Figure 27-9. Data Direction Register C (DDRC)
Bit 0
DDRC0
0
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, PTC2 is under
the control of MCLKEN. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRC[4:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins
as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Figure 27-10 shows the port C I/O logic.
READ DDRC ($0006)
WRITE DDRC ($0006)
RESET
WRITE PTC ($0002)
DDRCx
PTCx
PTCx
READ PTC ($0002)
Figure 27-10. Port C I/O Circuit
When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a
logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 27-3 summarizes the operation of the port C pins.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
321