MC68HC908AT32 Datasheet, PDF (133/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 15
External Interrupt (IRQ)
15.1 Introduction
This section describes the non-maskable external interrupt (IRQ) input.
15.2 Features
Features include:
• Dedicated external interrupt pin (IRQ1/V_PP)
• Hysteresis buffer
• Programmable edge-only or edge- and level-interrupt sensitivity
• Automatic interrupt acknowledge
15.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 15-1 shows the
structure of the IRQ module.
Interrupt signals on the IRQ1/V_PP pin are latched into the IRQ1 latch. An interrupt latch remains set until
one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
• Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge
bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK1 bit clears the
IRQ1 latch.
• Reset — A reset automatically clears both interrupt latches.
The external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge
and low-level triggered. The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ1/V_PP pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software
clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both
of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
133