MC68HC908AT32 Datasheet, PDF (342/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller-Digital (BDLC-D)
ACTIVE
TRANSMITTER A
PASSIVE
0
1
1
1
TRANSMITTER A DETECTS
AN ACTIVE STATE ON
THE BUS AND STOPS
TRANSMITTING
0
1
1
0
0
ACTIVE
TRANSMITTER B
PASSIVE
ACTIVE
J1850 BUS
PASSIVE
0
1
1
0
0
TRANSMITTER B WINS
ARBITRATION AND
CONTINUES
TRANSMITTING
DATA DATA DATA
DATA DATA
SOF
BIT 1 BIT 2 BIT 3
BIT 4 BIT 5
Figure 28-11. J1850 VPW Bitwise Arbitrations
During arbitration, or even throughout the transmitting message, when an opposite bit is detected,
transmission is stopped immediately unless it occurs on the eighth bit of a byte. In this case, the BDLC
automatically will append up to two extra logic 1 bits and then stop transmitting. These two extra bits will
be arbitrated normally and thus will not interfere with another message. The second logic 1 bit will not be
sent if the first loses arbitration. If the BDLC has lost arbitration to another valid message, then the two
extra logic 1s will not corrupt the current message. However, if the BDLC has lost arbitration due to noise
on the bus, then the two extra logic 1s will ensure that the current message will be detected and ignored
as a noise-corrupted message.
28.5 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC generation/checking, and error
detection. The protocol handler conforms to SAE J1850 Class B Data Communications Network
Interface.
NOTE
Freescale assumes that the reader is familiar with the J1850 specification
before reading this protocol handler description.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 28-12. BDLC Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
342
Freescale Semiconductor