MC68HC908AT32 Datasheet, PDF (95/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
Addr.
$001C
$001D
$001E
Register Name
Bit 7
6
5
4
PLL Control Register ^Read: _PLLIE
PLLF
PLLON
BCS
(PCTL) Write:
See page 101. _{Reset: 0}
0
1
0
PLL Bandwidth Control ^Read: _AUTO ^LOCK
ACQ
XLD
Register (PBWC) Write:
See page 103. _{Reset: 0}
0
0
0
PLL Programming Register ^Read:
(PPG) Write:
See page 104. _Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
= Unimplemented
Figure 8-2. I/O Register Summary
3
1
1
0
0
VRS7
0
2
1
1
0
0
VRS6
1
1
1
1
0
0
VRS5
1
Bit 0
1
1
0
0
VRS4
0
Table 8-1. I/O Register Address Summary
Register
Address
PCTL
$001C
PBWC
$001D
PPG
$001E
8.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator
circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50 percent and depends on external factors, including the crystal and
related external components.
An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the
external clock to the OSC1 pin and let the OSC2 pin float.
8.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
8.3.2.1 Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
95