MC68HC908AT32 Datasheet, PDF (272/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN Controller
23.13.3 MSCAN08 Bus Timing Register 0
Address:
Read:
Write:
Reset:
$0502
Bit 7
SJW1
0
6
SJW0
0
5
BRP5
0
4
BRP4
0
3
BRP3
0
2
BRP2
0
1
BRP1
0
Bit 0
BRP0
0
Figure 23-16. Bus Timing Register 0 (CBTR0)
SJW1 and SJW0 — Synchronization Jump Width Bit
The synchronization jump width (SJW) defines the maximum number of system clock (t_SCL) cycles by
which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the
bus (see Table 23-4).
Table 23-4. Synchronization Jump Width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization Jump Width
1 t_SCL cycle
2 t_SCL cycles
3 t_SCL cycles
4 t_SCL cycles
BRP5–BRP0 — Baud Rate Prescaler Bits
These bits determine the MSCAN08 system clock cycle time (t_SCL), which is used to build up the
individual bit timing, according to Table 23-5.
Table 23-5. Baud Rate Prescaler
BRP5
0
0
0
0
:
:
1
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler Value (P)
1
2
3
4
:
:
64
NOTE
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
MC68HC908AT32 Data Sheet, Rev. 3.1
272
Freescale Semiconductor