MC68HC908AT32 Datasheet, PDF (78/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
CLOCK
CONTROL
CLOCK GENERATORS
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 7-2. SIM Block Diagram
INTERRUPT SOURCES
CPU INTERFACE
Table 7-2 shows the internal signal names used in this section.
Table 7-2. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC908AT32 Data Sheet, Rev. 3.1
78
Freescale Semiconductor