MC68HC908AT32 Datasheet, PDF (273/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Programmer’s Model of Control Registers
23.13.4 MSCAN08 Bus Timing Register 1
Address:
Read:
Write:
Reset:
$0503
Bit 7
6
5
4
3
2
1
SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11
0
0
0
0
0
0
0
Figure 23-17. Bus Timing Register 1 (CBTR1)
Bit 0
TSEG10
0
SAMP — Sampling Bit
This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per
bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For
higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit.
1 = Three samples per bit
0 = One sample per bit
TSEG22–TSEG10 — Time Segment Bits
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point.
Table 23-6. Time Segment Syntax
Time Segment
SYNC_SEG
Transmit point
Sample point
Action
System expects transitions to occur on the bus during this
period.
A node in transmit mode will transfer a new value to the CAN
bus at this point.
A node in receive mode will sample the bus at this point. If the
three samples per bit option is selected then this point
marks the position of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 23-7.
TSEG13 TSEG12
0
0
0
0
0
0
0
0
.
.
.
.
1
1
TSEG11
0
0
1
1
.
.
1
Table 23-7. Time Segment Values
TSEG10
0
1
0
1
.
.
1
Time
Segment 1
1 t_SCL cycle
2 t_SCL cycles
3 t_SCL cycles
4 t_SCL cycles
.
.
16 t_SCL cycles
TSEG22
0
0
.
.
1
TSEG21 TSEG20
0
0
0
1
.
.
.
.
1
1
Time
Segment 2
1 t_SCL cycle
2 t_SCL cycles
.
.
8 t_SCL cycles
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of bus
clock cycles (t_SCL) per bit as shown in Table 23-7.
NOTE
The CBTR1 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
273