MC68HC908AT32 Datasheet, PDF (194/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface (TIMA-4)
If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA
before executing the WAIT instruction.
18.5.2 Stop Mode
The TIMA is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIMA counter. TIMA operation resumes when the MCU exits stop
mode.
18.6 TIMA during Break Interrupts
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 7.7.3 SIM Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
18.7 I/O Signals
Port D shares one of its pins with the TIMA. Port E shares two of its pins with the TIMA and port F shares
two of its pins with the TIMA. PTD6/ATD14/TACLK is an external clock input to the TIMA prescaler. The
four TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1, PTF0/TACH2, and PTF1/TACH3.
18.7.1 TIMA Clock Pin (PTD6/ATD14/TCLK)
PTD6/ATD14/TACLK is an external clock input that can be the clock source for the TIMA counter instead
of the prescaled internal bus clock. Select the PTD6/ATD14/TACLK input by writing logic 1s to the three
prescaler select bits, PS[2:0]. (See 18.8.1 TIMA Status and Control Register.) The minimum TCLK pulse
width, TCLK_LMIN or TCLK_HMIN, is:
------------------1-------------------
bus frequency
+
tSU
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TACLK is available as a general-purpose I/O pin or ADC channel when not used as the
TIMA clock input. When the PTD6/ATD14/TACLK pin is the TIMA clock input, it is an input regardless of
the state of the DDRD6 bit in data direction register D.
MC68HC908AT32 Data Sheet, Rev. 3.1
194
Freescale Semiconductor