MC68HC908AT32 Datasheet, PDF (346/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller-Digital (BDLC-D)
28.5.5.5 Summary
Table 28-2. BDLC J1850 Bus Error Summary
Error Condition
Transmission error
Cyclical redundancy check (CRC) error
Invalid symbol:
BDLC transmits,but receives invalid bits (noise)
Framing error
Bus short to V_DD
Bus short to GND
BDLC receives BREAK symbol
BDLC Function
For invalid bits or framing symbols on non-byte boundaries, invalid
symbol interrupt will be generated. BDLC stops transmission.
CRC error interrupt will be generated. The BDLC will wait for EOF.
The BDLC will abort transmission immediately. Invalid symbol interrupt
will be generated.
Invalid symbol interrupt will be generated. The BDLC will wait for end
of frame (EOF).
The BDLC will not transmit until the bus is idle. Invalid symbol interrupt
will be generated. EOF interrupt also must be seen before another
transmission attempt. Depending on length of the short, LOA flag
also may be set.
Thermal overload will shut down physical interface. Fault condition is
seen as invalid symbol flag. EOF interrupt must also be seen before
another transmission attempt.
Invalid symbol interrupt will be generated. The BDLC will wait for the
next valid start-of-frame (SOF).
28.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and consists of five user
registers.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 28-14. BDLC Block Diagram
MC68HC908AT32 Data Sheet, Rev. 3.1
346
Freescale Semiconductor