MC68HC908AT32 Datasheet, PDF (329/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 28
Byte Data Link Controller-Digital (BDLC-D)
28.1 Introduction
The byte data link controller (BDLC) provides access to an external serial communication multiplex bus,
operating according to the SAE J1850 protocol.
28.2 Features
Features of the byte data link controller (BDLC) module include:
• SAE J1850 Class B Data Communications Network Interface compatible and ISO compatible for
low-speed (<125 kbps) serial data communications in automotive applications
• 10.4 kbps variable pulse width (VPW) bit format
• Digital noise filter
• Collision detection
• Hardware cyclical redundancy check (CRC) generation and checking
• Two power-saving modes with automatic wakeup on network activity
• Polling or central processor unit (CPU) interrupts
• Block mode receive and transmit supported
• 4X receive mode, 41.6 kbps, supported
• Digital loopback mode
• Analog loopback mode
• In-frame response (IFR) types 0, 1, 2, and 3 supported
28.3 Functional Description
Figure 28-1 shows the organization of the BDLC module. The CPU interface contains the software
addressable registers and provides the link between the CPU and the buffers. The buffers provide storage
for data received and data to be transmitted onto the J1850 bus. The protocol handler is responsible for
the encoding and decoding of data bits and special message symbols during transmission and reception.
The multiplex (MUX) interface provides the link between the BDLC digital section and the analog physical
interface. The wave shaping, driving, and digitizing of data is performed by the physical interface.
Use of the BDLC module in message networking fully implements the SAE Standard J1850 Class B Data
Communication Network Interface specification.
NOTE
It is recommended that the reader be familiar with the SAE J1850 document
and ISO Serial Communication document prior to proceeding with this
section.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
329