MC68HC908AT32 Datasheet, PDF (338/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller-Digital (BDLC-D)
Break Signal (BREAK)
The BREAK signal is defined as a passive-to-active transition followed by an active period of at least
240 µs (see Figure 28-6(c)).
Start-of-Frame Symbol (SOF)
The SOF symbol is defined as passive-to-active transition followed by an active period 200 µs in length
(see Figure 28-6(d)). This allows the data bytes which follow the SOF symbol to begin with a passive
bit, regardless of whether it is a logic 1 or a logic 0.
End-of-Data Symbol (EOD)
The EOD symbol is defined as an active-to-passive transition followed by a passive period 200 µs in
length (see Figure 28-6(e)).
End-of-Frame Symbol (EOF)
The EOF symbol is defined as an active-to-passive transition followed by a passive period 280 µs in
length (see Figure 28-6(f)). If no IFR byte is transmitted after an EOD symbol is transmitted, after
another 80 µs the EOD becomes an EOF, indicating completion of the message.
Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 µs in length. The 20-µs IFS symbol contains no
transition, since when it is used it always appends to a 280-µs EOF symbol (see Figure 28-6(g)).
Idle
An idle is defined as a passive period greater than 300 µs in length.
28.4.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the J1850 bus have been defined to allow
for variations in oscillator frequencies. In many cases, the maximum time allowed to define a data bit or
symbol is equal to the minimum time allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol is being received is equal to a
single period of the MUX interface clock (t_BDLC), an apparent separation in these maximum time/minimum
time concurrences equals one cycle of t_BDLC.
This one clock resolution allows the BDLC to differentiate properly between the different bits and symbols.
This is done without reducing the valid window for receiving bits and symbols from transmitters onto the
J1850 bus, which has varying oscillator frequencies.
In Huntsinger’s variable pulse-width (VPW) modulation bit encoding, the tolerances for both the passive
and active data bits received and the symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the minimum length of a passive logic 1,
and the maximum length of an active logic 0 is equal to the minimum length of a valid SOF symbol.
Invalid Passive Bit
See Figure 28-7(1). If the passive-to-active received transition beginning the next data bit or symbol
occurs between the active-to-passive transition beginning the current data bit (or symbol) and a, the
current bit would be invalid.
MC68HC908AT32 Data Sheet, Rev. 3.1
338
Freescale Semiconductor