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MC68HC908AT32 Datasheet, PDF (367/378 Pages) Freescale Semiconductor, Inc – Microcontrollers
29.10 CGM Acquisition/Lock Time Information
CGM Acquisition/Lock Time Information
Description(1)
Symbol
Min
Manual mode time to stable
tACQ
—
Typ
(8 x VDDA)/(fXCLK x KACQ)
Manual stable to lock time
Manual acquisition time
Tracking mode entry frequency
tolerance
Acquisition mode entry
frequency tolerance
LOCK entry frequency
tolerance
LOCK exit frequency tolerance
Reference cycles per
acquisition mode
measurement
Reference cycles per tracking
mode measurement
Automatic mode time
to stable
Automatic stable to lock time
Automatic lock time
PLL jitter, deviation of average
bus frequency over 2 ms
tAL
tLock
DTRK
DUNT
DLOCK
DUNL
nACQ
—
—
0
± 6.3%
0
± 0.9%
—
(4 x VDDA)/(fXCLK x KTRK)
tACQ+tAL
—
—
—
—
32
nTRK
tACQ
tAL
tLock
—
128
nACQ/fXCLK
(8 x VDDA)/(fXCLK x KACQ)
nTRK/fXCLK
—
(4 x VDDA)/(fXCLK x KTRK)
tACQ+tAL
0
—
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, unless otherwise noted.
2. GBNT guaranteed but not tested
Max
—
—
—
± 3.6%
Notes
If CF chosen
correctly
If CF chosen
correctly
± 7.2%
± 0.9%
± 1.8%
—
—
—
—
± (fCRYS)
x (.025%)
x (N/4)
If CF chosen
correctly
If CF chosen
correctly
N = VCO Freq.
Mult.
(GBNT)(2)
29.11 Timer Module Characteristics
Characteristic
Input capture pulse width
Input clock pulse width
Symbol
tTIH, tTIL
tTCH, tTCL
Min
125
(1/fOP) + 5
Max
—
—
Unit
ns
ns
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
367