MC68HC908AT32 Datasheet, PDF (332/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller-Digital (BDLC-D)
28.3.1.3 Run Mode
This mode is entered from reset mode after all MCU reset sources are no longer asserted. Run mode is
entered from the BDLC wait mode whenever activity is sensed on the J1850 bus.
Run mode is entered from the BDLC stop mode whenever network activity is sensed, although messages
will not be received properly until the clocks have stabilized and the CPU is also in run mode.
In this mode, normal network operation takes place. The user should ensure that all BDLC transmissions
have ceased before exiting this mode.
28.3.1.4 BDLC Wait Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
WAIT instruction and if the WCM bit in the BCR1 register is cleared previously.
In this mode, the BDLC internal clocks continue to run. The first passive-to-active transition of the bus
generates a CPU interrupt request from the BDLC, which wakes up the BDLC and the CPU. In addition,
if the BDLC receives a valid end-of-frame (EOF) symbol while operating in wait mode, then the BDLC also
will generate a CPU interrupt request, which wakes up the BDLC and the CPU. See 28.7.1 Wait Mode.
28.3.1.5 BDLC Stop Mode
This power-conserving mode is entered automatically from run mode whenever the CPU executes a
STOP instruction or if the CPU executes a WAIT instruction and the WCM bit in the BCR1 is set
previously.
In this mode, the BDLC internal clocks are stopped but the physical interface circuitry is placed in a
low-power mode and awaits network activity. If network activity is sensed, then a CPU interrupt request
will be generated, restarting the BDLC internal clocks. See 28.7.2 Stop Mode.
28.3.1.6 Digital Loopback Mode
When a bus fault has been detected, the digital loopback mode is used to determine if the fault condition
is caused by failure in the node’s internal circuits or elsewhere in the network, including the node’s analog
physical interface. In this mode, the transmit digital output pin (BDTxD) and the receive digital input pin
(BDRxD) of the digital interface are disconnected from the analog physical interface and tied together to
allow the digital portion of the BDLC to transmit and receive its own messages without driving the J1850
bus.
28.3.1.7 Analog Loopback Mode
Analog loopback mode is used to determine if a bus fault has been caused by a failure in the node’s
off-chip analog transceiver or elsewhere in the network. The BDLC analog loopback mode does not
modify the digital transmit or receive functions of the BDLC. It does, however, ensure that once analog
loopback mode is exited, the BDLC will wait for an idle bus condition before participation in network
communication resumes. If the off-chip analog transceiver has a loopback mode, it usually causes the
input to the output drive stage to be looped back into the receiver, allowing the node to receive messages
it has transmitted without driving the J1850 bus. In this mode, the output to the J1850 bus typically is high
impedance. This allows the communication path through the analog transceiver to be tested without
interfering with network activity. Using the BDLC analog loopback mode in conjunction with the analog
transceiver’s loopback mode ensures that, once the off-chip analog transceiver has exited loopback
mode, the BCLD will not begin communicating before a known condition exists on the J1850 bus.
MC68HC908AT32 Data Sheet, Rev. 3.1
332
Freescale Semiconductor