MC68HC908AT32 Datasheet, PDF (98/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
4. Calculate the VCO frequency, f_VCLK.
f_VCLK = N × f_RCLK
Example: f_VCLK = 8 × 4 MHz = 32 MHz
5. Calculate the bus frequency, f_Bus, and compare f_Bus with f_BUSDES.
f_Bus
=
f_VCLK
4
Example:
f_Bus
=
32
MHz
4
= 8 MHZ
6. If the calculated f_Bus is not within the tolerance limits of the application, select another f_BUSDEs or
another f_RCLK.
7. Using the value 4.9152 MHz for f_NOM, calculate the VCO linear range multiplier, L. The linear range
multiplier controls the frequency range of the PLL.
⎛ ^fVCLK⎞
L
=
R
oun
d⎜
⎝
-f--N-----O----M-----_⎠⎟
Example:
L
=
------3----2-----M-----H----z-------
4.9152 MHz
=
7
8. Calculate the VCO center-of-range frequency, f_VRS. The center-of-range frequency is the midpoint
between the minimum and maximum frequencies attainable by the PLL.
f_VRS = L × f_NOM
Example: f_VRS = 7 × 4.9152 MHz = 34.4 MHz
NOTE
For proper operation,
f_VRS – f_VCLK
≤
-^f-^N----^O-----^M---
2
.
Exceeding the recommended maximum bus frequency or VCO frequency
can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent
of N.
b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent
of L.
MC68HC908AT32 Data Sheet, Rev. 3.1
98
Freescale Semiconductor