MC68HC908AT32 Datasheet, PDF (304/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface (TIM-6)
OVERFLOW
OVERFLOW
PERIOD
PTEx/TCHx
OVERFLOW
OVERFLOW
OVERFLOW
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 25-8. CHxMAX Latency
25.8.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of the input capture function or the
output compare value of the output compare function. The state of the TIMA channel registers after reset
is unknown.
In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the TIMA channel x registers
(TCHxH) inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of the TIMA channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Register Name and Address: TACH0H — $0027
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH0L — $0028
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH1H — $002A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Indeterminate after reset
Register Name and Address: TACH1L — $002B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 25-9. TIMA Channel Registers (TACH0H/L–TACH3H/L)
MC68HC908AT32 Data Sheet, Rev. 3.1
304
Freescale Semiconductor