MC68HC908AT32 Datasheet, PDF (61/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
5.3.7 EEPROM Control Register
This read/write register controls programming/erasing of the array.
Address: $FE1D
Bit 7
6
5
4
3
2
1
Read:
0
EERAS1 EERAS0
0
EEBCLK
EEOFF
EELAT
Write:
1
0
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 5-1. EEPROM Control Register (EECR)
Bit 0
EEPGM
0
EEBCLK — EEPROM Bus Clock Enable Bit
This read/write bit determines which clock will be used to drive the internal charge pump for
programming/erasing. Reset clears this bit.
1 = Bus clock drives charge pump
0 = Internal RC oscillator drives charge pump
NOTE
Using the internal RC oscillator for applications in the 3- to 5-V range is
recommended.
EEOFF — EEPROM Power Down Bit
This read/write bit disables the EEPROM module for lower power consumption. Any attempts to
access the array will give unpredictable results. Reset clears this bit.
1 = Disable EEPROM array
0 = Enable EEPROM array
NOTE
The EEPROM requires a recovery time, t_EEOFF, to stabilize after clearing
the EEOFF bit.
EERAS1 and EERAS0 — Erase Bits
These read/write bits set the erase modes. Reset clears these bits. See Table 5-3.
Table 5-3. EEPROM Program/Erase Mode Select
EEBPx
0
0
0
0
1
X = don’t care
EERAS1
0
0
1
1
X
EERA0
0
1
0
1
X
MODE
Byte program
Byte erase
Block erase
Bulk erase
No erase/program
EELAT — EEPROM Latch Control Bit
This read/write bit latches the address and data buses for programming the EEPROM array. EELAT
cannot be cleared if EEPGM is still set. Reset clears this bit.
1 = Buses configured for EEPROM programming
0 = Buses configured for normal read operation
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
61