MC68HC908AT32 Datasheet, PDF (114/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Break Module (BRK)
IAB[15:8]
IAB[15:0]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BREAK
IAB[7:0]
Figure 11-1. Break Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
$FE0C
Break Address Register High (BRKH)
See page 116.
Write:
Bit 15
14
13
12
11
10
9
Bit 8
Reset: 0
0
0
0
0
0
0
0
Read:
$FE0D
Break Address Register Low (BRKL)
See page 116.
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Reset: 0
0
0
0
0
0
0
0
$FE0E
Break Status and Control ^Read: _{BRKE BRKA}
0
0
0
0
0
0
Register (BRKSCR) Write:
See page 115. _{Reset: 0}
0
0
0
0
0
0
0
= Unimplemented
Figure 11-2. I/O Register Summary
Table 11-1. I/O Register Address Summary
Register
Address
BRKH
$FE0C
BRKL
$FE0D
BSCR
$FE0E
11.3.1 Flag Protection during Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the
break state.
11.3.2 CPU during Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
MC68HC908AT32 Data Sheet, Rev. 3.1
114
Freescale Semiconductor