MC68HC908AT32 Datasheet, PDF (115/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

11.3.3 TIM during Break Interrupts
A break interrupt stops the timer counter.
Low-Power Modes
11.3.4 COP during Break Interrupts
The COP is disabled during a break interrupt when V_DD + V_Hi is present on the RST pin.
11.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
11.4.1 Wait Mode
If enabled, the break module is active in wait mode. The SIM break stop/wait bit (SBSW) in the SIM break
status register indicates whether wait was exited by a break interrupt. If so, the user can modify the return
address on the stack by subtracting one from it. See 7.7.1 SIM Break Status Register.
11.4.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states. A break interrupt will cause an exit from stop mode and sets the SBSW bit in the SIM break status
register.
11.5 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
11.5.1 Break Status and Control Register
The break status and control register contains break module enable and status bits.
Address: $FE0E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BRKE BRKA
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
115