MC68HC908AT32 Datasheet, PDF (352/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Byte Data Link Controller-Digital (BDLC-D)
HEADER
DATA FIELD
CRC
TYPE 0 — NO IFR
HEADER
DATA FIELD
CRC
NB ID
TYPE 1 — SINGLE BYTE TRANSMITTED FROM A SINGLE RESPONDER
HEADER
DATA FIELD
CRC
NB ID1
ID N
TYPE 2 — SINGLE BYTE TRANSMITTED FROM MULTIPLE RESPONDERS
HEADER
DATA FIELD
CRC
NB
IFR DATA FIELD
CRC
(OPTIONAL)
TYPE 3 — MULTIPLE BYTES TRANSMITTED FROM A SINGLE RESPONDER
NB = Normalization Bit
ID = Identifier, usually the physical address of the responder(s)
Figure 28-18. Types of In-Frame Response (IFR)
TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3) Bit
The TMIFR1 bit requests the BDLC to transmit the byte in the BDLC data register (BDR) as the first
byte of a multiple byte IFR with CRC or as a single byte IFR with CRC. Response IFR bytes are still
subject to J1850 message length maximums (see 28.4.2 J1850 Frame Format). See Figure 28-18
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
has been received, the BDLC will attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into
the BDR. After TEOD has been set and the last IFR byte has been transmitted, the CRC byte
is transmitted.
0 = The TMIFR1 bit will be cleared automatically, once the BDLC has successfully transmitted the
CRC byte and EOD symbol, by the detection of an error on the multiplex bus or by a transmitter
underrun caused when the programmer does not write another byte to the BDR after the TDRE
interrupt.
If the TMIFR1 bit is set, the BDLC will attempt to transmit the normalization symbol followed by the byte
in the BDR. After the byte in the BDR has been loaded into the transmit shift register, a TDRE interrupt
(see 28.6.4 BDLC State Vector Register) will occur similar to the main message transmit sequence.
The programmer should then load the next byte of the IFR into the BDR for transmission. When the
last byte of the IFR has been loaded into the BDR, the programmer should set the TEOD bit in the
BDLC control register 2 (BCR2). This will instruct the BDLC to transmit a CRC byte once the byte in
the BDR is transmitted, and then transmit an EOD symbol, indicating the end of the IFR portion of the
message frame.
However, if the programmer wishes to transmit a single byte followed by a CRC byte, the programmer
should load the byte into the BDR before the EOD symbol has been received, and then set the TMIFR1
bit. Once the TDRE interrupt occurs, the programmer should then set the TEOD bit in the BCR2. This
will result in the byte in the BDR being the only byte transmitted before the IFR CRC byte, and no TDRE
interrupt will be generated.
MC68HC908AT32 Data Sheet, Rev. 3.1
352
Freescale Semiconductor