MC68HC908AT32 Datasheet, PDF (293/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel
3. The output compare value in the TIMA channel 2 registers initially controls the output on the
PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to
synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA
channel registers (2 or 3) that control the output are the ones written to last. TASC2 controls and monitors
the buffered output compare function, and TIMA channel 3 status and control register (TASC3) is unused.
While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the
PTF2/TACH4 pin. The TIMA channel registers of the linked pair alternately control the output.
Setting the MS4B bit in TIMA channel 4 status and control register (TSC4) links channel 4 and channel
5. The output compare value in the TIMA channel 4 registers initially controls the output on the
PTF2/TACH4 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to
synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA
channel registers (4 or 5) that control the output are the ones written to last. TASC4 controls and monitors
the buffered output compare function, and TIMA channel 5 status and control register (TASC5) is unused.
While the MS4B bit is set, the channel 5 pin, PTF3/TACH5, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output compares.
25.3.4 Pulse-Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM
signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 25-3 shows, the output compare value in the TIMA channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA
to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMA to
set the pin if the state of the PWM pulse is logic 0.
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
PTEx/TCHx
PULSE
WIDTH
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 25-3. PWM Period and Pulse Width
OUTPUT
COMPARE
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
293