MC68HC908AT32 Datasheet, PDF (220/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Modulo Timer (TIM)
Address
Register Name
Bit 7
6
5
4
3
TIM Status and Control ^{Read: TOF}
TOIE TSTOP
0
0
$004B
Register (TSC) Write: 0
TRST
See page 222. _Reset:
0
0
1
0
0
TIM Counter Register ^{Read: Bit 15}
14
13
12
11
$004C
High (TCNTH) Write:
See page 223. _Reset:
0
0
0
0
0
TIM Counter Register ^{Read: Bit 7}
6
5
4
3
$004D
Low (TCNTL) Write:
See page 223. _Reset:
0
0
0
0
0
TIM Counter Modulo ^Read: _{Bit 15}
14
13
12
11
$004E Register High (TMODH) Write:
See page 224. _Reset:
1
1
1
1
1
TIM Counter Modulo ^Read: _{Bit 7}
6
5
4
3
$004F Register Low (TMODL) Write:
See page 224. _Reset:
1
1
1
1
1
= Unimplemented
Figure 20-2. TIM I/O Register Summary
2
1
Bit 0
PS2
PS1
PS0
0
0
0
10
9
Bit 8
0
0
0
2
1
Bit 0
0
0
0
10
9
Bit 8
1
1
1
2
1
Bit 0
1
1
1
20.4 TIM Counter Prescaler
The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PS[2:0], in the status and control register select the
TIM clock source.
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the periodic interrupt. The TIM overflow flag (TOF) is set when the TIM counter value rolls
over to $0000 after matching the value in the TIM counter modulo registers. The TIM interrupt enable bit,
TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
20.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
20.5.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
MC68HC908AT32 Data Sheet, Rev. 3.1
220
Freescale Semiconductor