MC68HC908AT32 Datasheet, PDF (119/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

12.3.1 Entering Monitor Mode
Table 12-1 shows the pin conditions for entering monitor mode.
Table 12-1. Mode Selection
Functional Description
Mode
CGMOUT
Bus
Frequency
V_DD +
V_Hi(1)
1 0 1 1 Monitor
C-----G----M-----X-----C----L---K--- _or C-----G----M-----V-----C----L---K---
2
2
C-----G----M------O----U----T---
2
V_DD +
V_Hi(1)
1 0 1 0 Monitor
CGMXCLK
C-----G----M------O----U----T---
2
1. For V_Hi, see 29.4 5.0-Volt DC Electrical Characteristics and 29.1 Maximum Ratings.
Enter monitor mode by either:
• Executing a software interrupt instruction (SWI) or
• Applying a logic 0 and then a logic 1 to the RST pin.
The MCU sends a break signal (10 consecutive logic 0s) to the host computer, indicating that it is ready
to receive a command. The break signal also provides a timing reference to allow the host to determine
the necessary baud rate.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt. The alternate vectors are in the
$FE page instead of the $FF page and allow code execution from the internal monitor firmware instead
of user code. The COP module is disabled in monitor mode as long as V_DD + V_Hi (see 29.4 5.0-Volt DC
Electrical Characteristics) is applied to either the IRQ pin or the V_DD pin. See Chapter 7 System
Integration Module (SIM) for more information on modes of operation.
NOTE
Holding the PTC3 pin low when entering monitor mode causes a bypass of
a divide-by-two stage at the oscillator. The CGMOUT frequency is equal to
the CGMXCLK frequency, and the OSC1 input directly generates internal
bus clocks. In this case, the OSC1 signal must have a 50 percent duty cycle
at maximum bus frequency.
Table 12-2 is a summary of the differences between user mode and monitor mode.
Table 12-2. User and Monitor Mode Differences
Modes
User
Monitor
COP
Enabled
Disabled⁽¹⁾
Reset
Vector
High
$FFFE
$FEFE
Functions
Reset
Vector
Low
Break
Vector
High
$FFFF $FFFC
$FEFF $FEFC
Break
Vector
Low
$FFFD
$FEFD
SWI
Vector
High
$FFFC
$FEFC
SWI
Vector
Low
$FFFD
$FEFD
1. If the high voltage (V_DD + V_Hi) is removed from the IRQ1/V_PP pin while in monitor mode,
the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by
the COPD bit in the configuration register. (See 29.4 5.0-Volt DC Electrical
Characteristics.)
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
119