MC68HC908AT32 Datasheet, PDF (131/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

LVI Interrupts
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the LVI_TRIPF voltage for 32 to 40
CGMXCLK cycles. (See Table 14-1.) Reset clears the LVIOUT bit.
Table 14-1. LVIOUT Bit Indication
V_DD
At Level:
V_DD > LVI_TRIPR
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
LVI_TRIPF < V_DD < LVI_TRIPR
For Number of
CGMXCLK Cycles:
Any
< 32 CGMXCLK cycles
Between 32 and 40
CGMXCLK cycles
> 40 CGMXCLK cycles
Any
LVIOUT
0
0
0 or 1
1
Previous value
14.5 LVI Interrupts
The LVI module does not generate interrupt requests.
14.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
14.6.1 Wait Mode
With the LVIPWR bit in the configuration register programmed to logic 0, the LVI module is active after a
WAIT instruction.
With the LVIRST bit in the configuration register programmed to logic 0, the LVI module can generate a
reset and bring the MCU out of wait mode.
14.6.2 Stop Mode
With the LVISTOP and LVIPWR bits in the configuration register programmed to a logic 0, the LVI module
will be active after a STOP instruction. Because CPU clocks are disabled during stop mode, the LVI trip
must bypass the digital filter to generate a reset and bring the MCU out of stop.
With the LVIPWR bit in the configuration register programmed to logic 0 and the LVISTOP bit at a logic
1, the LVI module will be inactive after a STOP instruction.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
131