MC68HC908AT32 Datasheet, PDF (337/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

ACTIVE
PASSIVE
128 µs
BDLC MUX Interface
OR
64 µs
(A) LOGIC 0
ACTIVE
PASSIVE
128 µs
OR
64 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(B) LOGIC 1
≥ 240 µs
200 µs
200 µs
(C) BREAK
280 µs
(D) START OF FRAME
300 µs
20 µs
(E) END OF DATA
IDLE > 300 µs
(F) END OF FRAME
(G) INTER-FRAME
SEPARATION
(H) IDLE
Figure 28-6. J1850 VPW Symbols with Nominal Symbol Times
Each message will begin with an SOF symbol, an active symbol, and, therefore, each data byte (including
the CRC byte) will begin with a passive bit, regardless of whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the following descriptions are typical values at a 10.4-kbps bit rate. EOF,
EOD, IFS, and IDLE, however, are not driven J1850 bus states. They are passive bus periods observed
by each node’s CPU.
Logic 0
A logic 0 is defined as either:
– An active-to-passive transition followed by a passive period 64 µs in length, or
– A passive-to-active transition followed by an active period 128 µs in length
See Figure 28-6(a).
Logic 1
A logic 1 is defined as either:
– An active-to-passive transition followed by a passive period 128 µs in length, or
– A passive-to-active transition followed by an active period 64 µs in length
See Figure 28-6(b).
Normalization Bit (NB)
The NB symbol has the same property as a logic 1 or a logic 0. It is only used in IFR message
responses.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
337