MC68HC908AT32 Datasheet, PDF (82/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
OSC1
PORRST
CGMXCLK
4096
CYCLES
32
CYCLES
32
CYCLES
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 7-7. POR Recovery
7.3.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status
register (SRSR) if the COPD bit in the CONFIG-1 register is at logic 0. See Chapter 13 Computer
Operating Properly Module (COP).
7.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the CONFIG-1 register is logic 0, the SIM treats the STOP instruction as
an illegal opcode and causes an illegal opcode reset.
7.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset.
7.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V_DD voltage falls to the V_LVII
voltage. The LVI bit in the SIM reset status register (SRSR) is set and a chip reset is asserted if the
LVIPWRD and LVIRSTD bits in the CONFIG-1 register are at logic 0. The RST pin will be held low until
the SIM counts 4096 CGMXCLK cycles after V_DD rises above V_LVIR. Another 64 CGMXCLK cycles later,
the CPU is released from reset to allow the reset vector sequence to occur. See Chapter 14 Low-Voltage
Inhibit (LVI).
MC68HC908AT32 Data Sheet, Rev. 3.1
82
Freescale Semiconductor