MC68HC908AT32 Datasheet, PDF (87/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Power Modes
by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how
each module is affected by the break state.
7.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a two-step clearing mechanism — for example,
a read of one register followed by the read or write of another — are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
7.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-power mode for standby situations. The
SIM holds the CPU in a non-clocked state. The operation of each of these modes is described here. Both
STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
7.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while one set of peripheral clocks continues to run. Figure 7-12
shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the
configuration register is logic 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 7-12. Wait Mode Entry Timing
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
87