MC68HC908AT32 Datasheet, PDF (51/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4
FLASH Memory
4.1 Introduction
This section describes the operation of the embedded FLASH memory. This memory can be read,
programmed, and erased from a single external supply through the use of on-board charge pumps for
program and erase.
4.2 Functional Description
The FLASH memory is an array of 32,256 bytes with an additional 48 bytes of user vectors and one byte
of block protection. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program
and erase operations are facilitated through control bits in a memory mapped register. Details for these
operations appear later in this section. The address ranges for the user memory and vectors are:
• $8000–$FDFF
• $FF80 (block protect register)
• $FFD0–$FFFF (These locations are reserved for user-defined interrupt and reset vectors.)
Programming tools are available from Freescale. Contact your local Freescale representative for more
information.
NOTE
A security feature prevents viewing of the FLASH contents.⁽¹⁾
4.3 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program, erase, and verify operations.
Address: $FE0B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
FDIV1
Write:
FDIV0
BLK1
BLK0
HVEN
VERF ERASE
PGM
Reset: 0
0
0
0
0
0
0
0
Figure 4-1. FLASH Control Register (FLCR)
FDIV1 — Frequency Divide Control Bit
This read/write bit together with FDIV0 selects the factor by which the charge pump clock is divided
from the system clock. See 4.4 Charge Pump Frequency Control.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
51