MC68HC908AT32 Datasheet, PDF (302/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface (TIM-6)
CHxF — Channel x Flag
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMA counter registers matches the value in the TIMA channel x registers.
When CHxIE = 0, clear CHxF by reading TIMA channel x status and control register with CHxF set,
and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due
to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA
channel 0, TIMA channel 2, and TIMA channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TACH1 pin to
general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and reverts TACH3 pin to
general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and reverts TACH5 pin to
general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation.
See Table 25-2.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin once PWM,
output compare mode, or input capture mode is enabled. (See Table 25-2.). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMA status and control register (TSC).
MC68HC908AT32 Data Sheet, Rev. 3.1
302
Freescale Semiconductor