MC68HC908AT32 Datasheet, PDF (110/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration Register (CONFIG-1)
NOTE
To have the LVI enabled in stop mode, the LVIPWR must be at a logic 0
and the LVISTOP bit must be at a logic 1. Take note that by enabling the
LVI in stop mode, the stop I_DD current will be higher and for compatibility
when using a MC68HC08AS20 a register bit will have to be written. See the
LVI section of the MC68HC08AS20 Advance Information.
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. See Chapter 14 Low-Voltage Inhibit (LVI).
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. See Chapter 14 Low-Voltage Inhibit (LVI).
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay. (See 7.6.2 Stop Mode.)
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS selects either the short COP timeout period or the long COP timeout period. See Chapter 13
Computer Operating Properly Module (COP).
1 = COP timeout period is 8,176 CGMXCLK cycles.
0 = COP timeout period is 262,128 CGMXCLK cycles.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 13 Computer Operating Properly Module (COP).
1 = COP module disabled
0 = COP module enabled
MC68HC908AT32 Data Sheet, Rev. 3.1
110
Freescale Semiconductor