MC68HC908AT32 Datasheet, PDF (261/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Link
23.8.2 CPU Wait Mode
The MSCAN08 module remains active during CPU wait mode. The MSCAN08 will stay synchronized to
the CAN bus and will generate enabled transmit, receive, and error interrupts to the CPU. Any such
interrupt will bring the MCU out of wait mode.
23.8.3 CPU Stop Mode
A CPU STOP instruction will stop the crystal oscillator, thus shutting down all system clocks. The user is
responsible for ensuring that the MSCAN08 is not active when the CPU goes into stop mode. To protect
the CAN bus system from fatal consequences of violations to this rule, the MSCAN08 will drive the TxCAN
pin into a recessive state.
The recommended procedure is to bring the MSCAN08 into sleep mode before the CPU STOP instruction
is executed.
23.8.4 Programmable Wakeup Function
The MSCAN08 can be programmed to apply a low-pass filter function to the RxCAN input line while in
internal sleep mode (see information on control bit WUPM in 23.13.1 MSCAN08 Module Control
Register). This feature can be used to protect the MSCAN08 from wakeup due to short glitches on the
CAN bus lines. Such glitches can result from electromagnetic inference within noisy environments.
23.9 Timer Link
The MSCAN08 will generate a timer signal whenever a valid frame has been received. Because the CAN
specification defines a frame to be valid if no errors occurred before the EOF field has been transmitted
successfully, the timer signal will be generated right after the EOF. A pulse of one bit time is generated.
As the MSCAN08 receiver engine also receives the frames being sent by itself, a timer signal also will be
generated after a successful transmission.
The previously described timer signal can be routed into the on-chip timer interface module (TIM). Under
the control of the timer link enable (TLNKEN) bit in the CMCR0, this signal will be connected to the timer
n channel m input.
NOTE
The timer channel being used for the timer link is integration dependent.
After timer n has been programmed to capture rising edge events, it can be used to generate 16-bit time
stamps which can be stored under software control with the received message.
23.10 Clock System
Figure 23-7 shows the structure of the MSCAN08 clock generation circuitry and its interaction with the
clock generation module (CGM). With this flexible clocking scheme the MSCAN08 is able to handle CAN
bus rates ranging from 10 kbps up to 1 Mbps.
The clock source flag (CLKSRC) in the MSCAN08 module control register (CMCR1) (see 23.13.1
MSCAN08 Module Control Register) defines whether the MSCAN08 is connected to the output of the
crystal oscillator or to the PLL output.
MC68HC908AT32 Data Sheet, Rev. 3.1
Freescale Semiconductor
261