MC68HC908AT32 Datasheet, PDF (242/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MC68HC08AZ32 Emulator Input/Output Ports
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 22-13 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDx
READ PTD ($0003)
Figure 22-13. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 22-4 summarizes the operation of the port D pins.
Table 22-4. Port D Pin Functions
DDRD PTD
Bit
Bit
I/O Pin
Mode
Accesses
to DDRD
Read/Write
Accesses to PTD
Read
Write
0
X
Input, Hi-Z
DDRD[7:0]
Pin
PTD[7:0]⁽¹⁾
1
X
Output
DDRD[7:0]
PTD[7:0]
PTD[7:0]
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
MC68HC908AT32 Data Sheet, Rev. 3.1
242
Freescale Semiconductor