MC68HC908AT32 Datasheet, PDF (278/378 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN Controller
IDHIT1–IDHIT0— Identifier Acceptance Hit Indicator Flags
The MSCAN08 sets these flags to indicate an identifier acceptance hit (see 23.5 Identifier Acceptance
Filter). Table 23-7 summarizes the different settings.
Table 23-9. Identifier Acceptance Hit Indication
IDHIT1
0
0
1
1
IDHIT0
0
1
0
1
Identifier Acceptance Hit
Filter 0 hit
Filter 1 hit
Filter 2 hit
Filter 3 hit
The IDHIT indicators are always related to the message in the foreground buffer. When a message gets
copied from the background to the foreground buffer, the indicators are updated as well.
NOTE
The CIDAC register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
23.13.10 MSCAN08 Receive Error Counter
Address: $050E
Bit 7
Read: RXERR7
6
RXERR6
5
RXERR5
4
RXERR4
3
RXERR3
2
RXERR2
1
RXERR1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 23-23. Receiver Error Counter (CRXERR)
Bit 0
RXERR0
0
This register reflects the status of the MSCAN08 receive error counter. The register is read only.
23.13.11 MSCAN08 Transmit Error Counter
Address: $050F
Read:
Write:
Reset:
Bit 7
TXERR7
0
6
5
TXERR6 TXERR5
0
0
= Unimplemented
4
TXERR4
0
3
TXERR3
0
2
TXERR2
0
1
TXERR1
0
Figure 23-24. Transmit Error Counter (CTXERR)
Bit 0
TXERR0
0
This register reflects the status of the MSCAN08 transmit error counter. The register is read only.
NOTE
For both error counters, there is no hardware synchronization between the
write accesses to those registers from the MSCAN08 side and the read
accesses by the CPU. It is the user’s responsibility to verify that a stable
value has been read by executing a second validation read and comparing
the two values.
MC68HC908AT32 Data Sheet, Rev. 3.1
278
Freescale Semiconductor